Prototype: Development updates

The development process of ACSMA (Advanced Configurable Scrypt Mining Architecture)


We are still perfectly on track to release the FPGA prototype in less than 25 days from now. It is quite a monumental task to set up a powerful miner which is fast and reliable. We have already passed the biggest hurdles and we are well on our way to complete the final tasks within our set time frame.

Bellow are the details of our development :

Functional simulation:

We studied several approaches in order to develop a powerful and configurable architecture that is capable of mining different new SCRYPT oriented toward crypotcurrencies.

The development started by structuring the architecture in high level language which is called HLS conversion to obtain RTL code. We obtained, for purposes of FPGA prototyping, 200K lines of RTL code that were tested in Functional Analysis. This phase was tested with a real cycle simulator.

Real simulation with Questa Advanced Simulator. The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Platform; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs

After Functional simulation, we have now an idea about the resources required to prototype on the FPGA platform. The Scrypt algorithm requires a lot of memory. In a few words the trick is “the faster you can run the algorithm ; the  faster you will produce data ; the more memories you will require”.

So, as stated earlier,  in order to test an architecture like ACSMA, we needed a FPGA system with a lot of embedded blocks of memory. In our case 80Mbits were the minimum required and only the Achronix FPGA was fast enough and had that big memory.

Mapping Phase:

The next processing phases are physically porting all the RTL code into FPGA logic and memories.

After logic synthesis we started to see our developing architecture in terms of logic primitives.

Our developing architecture in terms of logic primitives


The Mapping phase is a phase where all is optimized and connected. Now we have converted all language code into FPGA resources and we need only to verify that the conversion process is right and the behavior is equivalent to the functional code we started with.

This is as you can see our design in terms of Achronix logic elements memory blocks, LUTS ,ALUS etc.


After Synthesis and mapping is done. The last and more time consuming phase starts:

Placing and Routing Phase:


Here our logic blocks are given a pysical location inside the big FPGA fabric

This phase is iterative as it is very computationally intensive, and demands are very limited to the human intervention.

Only directives are given at the start of the process of routing to guide the routing algorithm.

The fpga pins location are tested in the Achronix platform
Here is the Achronix test platform alongside, a PCDUINO3 which will be used as a host miner.
Several host platforms are currently considered for the final ASIC design : A Ti DSP , Parallella 16/64 cores and the PCDuino3 : All have USB connectivity.

After the prototype is ready, What is next?

After this phase, everything becomes easy - we’ll  just do the FPGA/ASIC conversion. The FPGA based design can be converted into an ASIC.

Preorders :

First of all, thank you for your patience. We appreciate it since, it has been a while that we updated you with our news.

Most importantly, we are glad to inform you that we are in our final stage of development. We are nearly reaching the testing phase. So, once our hardware is tested, our dear miners will have a large chance for preorder.


We love crypto

Ehsminer Team